1. Field of the Invention
The present invention is directed toward the field of clock synthesis, and more particularly toward generating multiple clock signals with different frequencies.
2. Art Background
Clock synthesis circuits are used to generate clock signals. Typically, the clock signals provide timing for operation of a circuit. In some applications, multiple timing references or clocks, which operate at different frequencies, are required. For example, some communication standards require operation of transmitter and receiver circuits at predetermined clock frequencies. If a circuit supports multiple timing references, then multiple clock synthesis circuits are used. Typically, each clock synthesis circuit includes a timing reference, such as a crystal. Thus, if multiple clock frequencies are generated, then multiple clock references are required. In addition, if the timing references are highly accurate, then the cost of the crystal is high. Accordingly, it is desirable to reduce the number of timing references used to generate multiple clock frequencies.
Some circuit applications require a variable frequency clock. In general, a variable frequency clock is a clock that changes frequency over time. One application to vary the clock frequency is spread spectrum clock generation. Some personal computers employ spread spectrum clock generation techniques to vary the clock frequency used for timing in an interface between a disk controller and a hard disk drive. The variable frequency for the timing clock helps reduce electromagnetic interference (EMI) that emanates from the personal computer. For the spread spectrum clock application, clock synthesis circuits must generate a variable output frequency. Typically, to achieve this, the clock synthesis circuits use a traditional phase locked loop. The phase locked loop includes a feed-forward divider that divides the reference clock by a variable, M. The output of the divider is then fed into a phase locked loop that multiplies the signal by a variable, N. To obtain greater frequency resolution in such a circuit, the value of the divider and multiplier (e.g., the variables N and M) must be increased. This, in turn, reduces the phase locked loop update rate, and thus limits the phase locked loop bandwidth so as to make the loop more susceptible to power supply, substrate and inherent device noise. Accordingly, it is desirable to generate a clock synthesis circuit capable of generating a variable frequency output, with high resolution while maintaining high loop bandwidth.